Struct ControlRegisters 

pub struct ControlRegisters {
    pub diagnostic_only: CurrentInstructionDiagnostics,
    pub n: Instruction,
    pub n_sym: Option<SymbolicInstruction>,
    pub p: Address,
    pub q: Address,
    pub k: Option<SequenceNumber>,
    spr: Address,
    pub index_regs: [Signed18Bit; 64],
    f_memory: [SystemConfiguration; 32],
    flags: SequenceFlags,
    current_sequence_is_runnable: bool,
    prev_hold: bool,
}

Registers from various elements of the TX-2.

This includes both programmer-accessible registers (Index registers for example) and non-programmer accessible registers (such as the N register).

Fields

diagnostic_only: CurrentInstructionDiagnostics

n: Instruction

Contents of the simulated N register.

n_sym: Option<SymbolicInstruction>

p: Address

The P register is the program counter for the current sequence.

q: Address

Contents of the simulaterd Q register.

k: Option<SequenceNumber>

The k register (User Guide section 4-3.1) holds the current sequence number (User Guide section 5-24). k is Option<SequenceNumber> in order to allow the (emulated) control unit to recognise a CODABO button as indicating a need to change sequence from the control unit’s initial state to sequence 0.

This likely doesn’t reflect the actual operation of the TX-2 very well, and better understanding of the real operation of the machine will likely change this.

I think that perhaps section 12-2.6.2 of Volume 2 of the technical manual may explain how the real TX-2 avoided this problem, but I don’t think I understand what that section says. The text is:

“”“12-2.6.2 XPS FLIP-FLOP LOGIC. This flip-floop inhibits the X Memory strobe pulse into X when the register selected has the same address or the current program counter, is not register 0, and this is the first reference to this register since the last sequence change. In this case all the cores of the register are clearered and only “junk” (with a 50-50 chance of a bad parity) would be strobed into X. If XPS¹, then a clear pulse is substituted for the strobe pulse.

The flip-flop is set whenever a sequence change occurs, and is cleared the first time thereafter that the program counter register is referenced during a PK cycle (if ever). See Fig 12-8.“”“

spr: Address

Start Point Register

index_regs: [Signed18Bit; 64]

Index registers.

Index register 0 is the Toggle Start point. Index registers 40-77 are program counters for the sequences.

The index registers form an 18-bit ring (as stated in the description of the AUX instruction) and are described on page 3-68 of the User Handbook (section 3-3.1) as being signed integers.

f_memory: [SystemConfiguration; 32]

the F memory

flags: SequenceFlags

The flags; these indicate which sequences are runnable.

current_sequence_is_runnable: bool

prev_hold: bool

prev_hold is set when the instruction we most previously executed had the “hold” bit set.

Implementations

impl ControlRegisters

fn new( configuration_memory_config: ConfigurationMemorySetup, ) -> ControlRegisters

fn previous_instruction_hold(&self) -> bool

fn set_spr(&mut self, addr: &Address)

fn get_index_register(&self, n: Unsigned6Bit) -> Signed18Bit

fn get_index_register_as_address(&mut self, n: Unsigned6Bit) -> Address

fn set_index_register(&mut self, n: Unsigned6Bit, value: &Signed18Bit)

fn set_index_register_from_address(&mut self, n: Unsigned6Bit, addr: &Address)

fn get_f_mem(&self, n: Unsigned5Bit) -> SystemConfiguration

pub fn current_flag_state(&self, seq: &Unsigned6Bit) -> bool

Trait Implementations

impl Debug for ControlRegisters

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl DiagnosticFetcher for &ControlRegisters

fn diagnostics(self) -> CurrentInstructionDiagnostics