pub enum AlarmDetails {
PSAL(u32, String),
OCSAL(Instruction, String),
QSAL(Instruction, BadMemOp, String),
IOSAL {
unit: Unsigned6Bit,
operand: Option<Unsigned18Bit>,
message: String,
},
MISAL {
affected_unit: Unsigned6Bit,
},
ROUNDTUITAL {
explanation: String,
bug_report_url: &'static str,
},
DEFERLOOPAL {
address: Unsigned18Bit,
},
BUGAL {
activity: BugActivity,
diagnostics: CurrentInstructionDiagnostics,
message: String,
},
}
Expand description
AlarmsDetails
variant names are from User’s Handbook section
5-2.2; full names are taken from section 10-2.5.1 (vol 2) of the
Technical Manual.
These acrronyms are upper case to follow the names in the TX-2 documentation.
§Unimplemented Alarms
Alarms we have not implemented:
Mnemonic | Description | Reason why It’s not Included |
---|---|---|
SYAL1 | Sync System Alarm (see User Handbook page 5-21). | Not yet implemented. |
SYAL2 | Sync System Alarm (see User Handbook page 5-21). | Not yet implemented. |
MPAL | M memory Parity Alarm | Parity errors are not emulated. |
NPAL | N memory Parity Alarm | Parity errors are not emulated. |
FPAL | F memory Parity Alarm | Parity errors are not emulated. |
XPAL | X memory Parity Alarm | Parity errors are not emulated. |
TSAL | T memory selection alarm | Indicates overcurrent in the T Memory. We have no hardware, so no overcurrent. |
USAL | U memory selection alarm | Indicates overcurrent in the T Memory. We have no hardware, so no overcurrent. |
Mousetrap | Stops the computer when there is a malfunction in the setting of the S-memory flip-flops (or perhaps other reasons chosen by the system maintainers). | Not required. |
L. G. Roberts memo of 1965-01-07 seems to indicate that another alarm, SPAL, was introduced later; see http://www.bitsavers.org/pdf/mit/tx-2/rcsri.org_library_tx2/TX2-Memos-General_196407.pdf.
Variants§
PSAL(u32, String)
P Memory Cycle Selection Alarm. This fires when we attempt to fetch an instruction (but not an operand) from an invalid address.
OCSAL(Instruction, String)
Operation Code Alarm. This fires when an instruction word containing an undefined operation code is read out of memory.
Section 10-2.5.3 of the TX-2 Technical Manual (Volume 2)
states that this can also happen when an AOP
instruction
specifies an undefined op code in bits N₂.₆-N₂.₁. An AOP
instruction is has opcode number 4, but with bits N₂.₈=0 and
N₂.₇=1 (instead of 00 which is the case for an IOS
instruction). So far however, we have not found any further
information about the interpretation of bits N₂.₆-N₂.₁ for
AOP
.
QSAL(Instruction, BadMemOp, String)
Q Memory Cycle Selecttion Alarm. Q register (i.e. data fetch address) is set to an invalid address.
IOSAL
In-Out Selection Alarm. I/O Alarm in IOS instruction; device broken/maintenance/nonexistent.
Fields
unit: Unsigned6Bit
The affected unit (as opposed to the sequence number currently executing).
MISAL
In-Out Miss Indication Alarm. Fires when some I/O unit has missed a data item. This generally indicates that the program is too slow for an I/O device. For example because it uses too many hold bits.
Fields
affected_unit: Unsigned6Bit
ROUNDTUITAL
Indicates that something is not implemented in the emulator. This alarm didn’t exist in the real TX-2.
DEFERLOOPAL
Loop in deferred addressing (detection of this is not a feature of the TX-2, this occurs only in the emulator).
Fields
address: Unsigned18Bit
address is some address within the loop.
BUGAL
There is a bug in the simulator.
Fields
activity: BugActivity
What were we doing?
diagnostics: CurrentInstructionDiagnostics
What instruction was executing?
Implementations§
Trait Implementations§
Source§impl Clone for AlarmDetails
impl Clone for AlarmDetails
Source§fn clone(&self) -> AlarmDetails
fn clone(&self) -> AlarmDetails
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
. Read more