pub(crate) struct TrapCircuit {
mode: Unsigned12Bit,
set_metabits_disabled: bool,
}
Fields§
§mode: Unsigned12Bit
§set_metabits_disabled: bool
Implementations§
Source§impl TrapCircuit
impl TrapCircuit
Sourceconst TRAP_ON_MARKED_INSTRUCTION: Unsigned12Bit
const TRAP_ON_MARKED_INSTRUCTION: Unsigned12Bit
When this bit is set in mode
, fetching an instruction word
whose metabit is set causes a trap to occur.
Sourceconst TRAP_ON_DEFERRED_ADDRESS: Unsigned12Bit
const TRAP_ON_DEFERRED_ADDRESS: Unsigned12Bit
When this bit is set in mode
, an instruction cycle which
uses a marked deferred address causes the TRAP flag to be
raised.
Sourceconst TRAP_ON_OPERAND: Unsigned12Bit
const TRAP_ON_OPERAND: Unsigned12Bit
When this bit is set in mode
, use of a marked operand causes
the TRAP flag to be raised soon afterward (within a few
instructions).
Sourceconst TRAP_ON_CHANGED_SEQUENCE: Unsigned12Bit
const TRAP_ON_CHANGED_SEQUENCE: Unsigned12Bit
When this bit is set, change of sequence number causes the TRAP flag to be raised. Change of sequence away from sequence 0o42 (the TRAP sequence itself) does not cause the flag to be raised).
Sourceconst SET_METABITS_OF_INSTRUCTIONS: Unsigned12Bit
const SET_METABITS_OF_INSTRUCTIONS: Unsigned12Bit
When this bit is set, fetching an instruction from a memory word causes the meta bit of that word to be set.
Sourceconst SET_METABITS_OF_DEFERRED_ADDRESSES: Unsigned12Bit
const SET_METABITS_OF_DEFERRED_ADDRESSES: Unsigned12Bit
When this bit is set, the metabit of all deferred addresses used will be set.
Sourceconst SET_METABITS_OF_OPERANDS: Unsigned12Bit
const SET_METABITS_OF_OPERANDS: Unsigned12Bit
When this bit is set, the metabits of memory words containing operands will be set.
pub(crate) const fn new() -> TrapCircuit
Sourcepub(crate) fn is_set_metabits_disabled(&self) -> bool
pub(crate) fn is_set_metabits_disabled(&self) -> bool
Query the hardware switch setting which would disable all setting of metabits.
Sourcepub(crate) fn set_metabits_disabled(&mut self, disable: bool)
pub(crate) fn set_metabits_disabled(&mut self, disable: bool)
Change the (emulated) hardware switch setting which (when
disable
is true) would disable all setting of metabits.
Sourcepub(crate) fn set_metabits_of_instructions(&self) -> bool
pub(crate) fn set_metabits_of_instructions(&self) -> bool
Indicate whether the machine should set the metabits of words from which it fetches instructions.
Sourcepub(crate) fn set_metabits_of_deferred_addresses(&self) -> bool
pub(crate) fn set_metabits_of_deferred_addresses(&self) -> bool
Indicate whether the machine should set the metabits of words from which it fetches deferred addresses.
Sourcepub(crate) fn set_metabits_of_operands(&self) -> bool
pub(crate) fn set_metabits_of_operands(&self) -> bool
Indicate whether the machine should set the metabits of words from which it fetches operands.
Sourcepub(crate) fn trap_on_marked_instruction(&self) -> bool
pub(crate) fn trap_on_marked_instruction(&self) -> bool
Indicate whether the TRAP flag should be raised during execution of an instruction whose metabit is set.
Sourcepub(crate) fn trap_on_deferred_address(&self) -> bool
pub(crate) fn trap_on_deferred_address(&self) -> bool
Indicate whether an instruction cycle which uses a marked deferred address causes the TRAP flag to be raised.
Sourcepub(crate) fn trap_on_operand(&self) -> bool
pub(crate) fn trap_on_operand(&self) -> bool
Indicate whether use of a marked operand causes the TRAP flag to be raised soon afterward (within a few instructions).
Sourcepub(crate) fn trap_on_changed_sequence(&self) -> bool
pub(crate) fn trap_on_changed_sequence(&self) -> bool
Indicate whether change of sequence number causes the TRAP flag to be raised. Change of sequence away from sequence 0o42 (the TRAP sequence itself) does not cause the flag to be raised).
Trait Implementations§
Source§impl Debug for TrapCircuit
impl Debug for TrapCircuit
Source§impl Unit for TrapCircuit
impl Unit for TrapCircuit
Source§fn read(
&mut self,
_ctx: &Context,
_diags: &CurrentInstructionDiagnostics,
) -> Result<MaskedWord, TransferFailed>
fn read( &mut self, _ctx: &Context, _diags: &CurrentInstructionDiagnostics, ) -> Result<MaskedWord, TransferFailed>
The TRAP unit doesn’t perform I/O but reads retain the cycle-left and dismiss features (See Users Handbook, section 4-15 (“TRAP”). Because it cycles left, it must be an “input” unit.
Source§fn write(
&mut self,
_ctx: &Context,
_source: Unsigned36Bit,
_diags: &CurrentInstructionDiagnostics,
) -> Result<Option<OutputEvent>, TransferFailed>
fn write( &mut self, _ctx: &Context, _source: Unsigned36Bit, _diags: &CurrentInstructionDiagnostics, ) -> Result<Option<OutputEvent>, TransferFailed>
I don’t know whether this is supposed to behave like an input unit or an output unit.
Source§fn poll(&mut self, ctx: &Context) -> UnitStatus
fn poll(&mut self, ctx: &Context) -> UnitStatus
Source§fn transfer_mode(&self) -> TransferMode
fn transfer_mode(&self) -> TransferMode
TransferMode
of the unit.